The working of power MOSFET during switching

A power MOSFET switches by using gate charge to control a conductive channel between drain and source. To understand the working of a power MOSFET, track gate-to-source voltage, drain-to-source voltage, and drain current together: the gate signal initiates the transition, while the load and circuit parasitics shape what happens at the drain.

Set up the power MOSFET switching waveform

A useful switching waveform shows gate-to-source voltage, drain-to-source voltage, and drain current on the same time base, alongside the load and current-commutation path. With those signals aligned, you can identify when the MOSFET begins conducting, carries load current, and blocks voltage.

Start with the circuit, not just the traces. Identify whether the device is a low-side or high-side switch, what the load is, and where current flows before and after each transition. An inductive load, for example, needs a path for its current when the MOSFET changes state; that path may include another switch, a diode, or a clamp, depending on the topology.

Then label the measurements:

• Measure gate-to-source voltage, VGS, at the device terminals if practical. The driver output is not necessarily the voltage present at the gate when current flows through gate resistance and parasitic inductance.
• Measure drain-to-source voltage, VDS, across the MOSFET. The difference between the bus voltage and VDS during conduction helps show the device’s on-state voltage drop.
• Measure drain current, ID, or a suitable current in the switching path. Confirm whether the measured current is the MOSFET current or load current; those can differ during commutation.
• Mark the commanded switching edge and the time scale. A longer view shows the full cycle; a faster view resolves the transition.

When interpreting applications with high-voltage conversion stages, keep other components in the current path in view too. For example, High Voltage Silicon Carbide Diodes may be relevant to a circuit’s commutation path, but their presence does not remove the need to identify the actual current route in the schematic.

A common pitfall is treating a gate waveform measured at the driver as the gate voltage at the MOSFET. Long traces or a remote probe reference can hide ringing and voltage differences. Record the probe location and reference point with each capture so another engineer can interpret the traces correctly.

Follow gate charge through turn-on

During turn-on, the driver supplies charge to the gate: VGS rises, the channel begins to conduct, and the Miller interval accompanies a change in VDS. Reading those stages in order helps separate channel formation from the drain-voltage transition.

Gate voltage does not jump instantly to its commanded level. The driver must move charge through the gate circuit, and the device’s capacitances affect how that charge is distributed over time. The resulting trace is a sequence, not a single on/off event. For broader context on interpreting these transitions, see MOSFET switching behavior.

Gate voltage rises to threshold

At the start of turn-on, the driver charges the gate and VGS rises. When it reaches the device’s threshold region, a channel begins to form and drain current can start to increase. Threshold voltage marks the onset of channel conduction under the conditions used for its specification; it does not mean the MOSFET is fully enhanced for the intended load current.

Check the device datasheet for the conditions attached to threshold voltage. It is not, by itself, a suitable gate-drive target or a direct indication of the on-resistance available in a design. The actual current and VDS depend on the gate voltage, device characteristics, load, and circuit.

If the current trace starts rising while VDS is still high, that can be part of the expected transition: the MOSFET is beginning to take current before the drain voltage has fallen. Avoid calling this interval steady-state conduction.

The Miller plateau shifts drain voltage

As turn-on proceeds, VGS may pause or rise more slowly while VDS falls. This is the Miller plateau: gate charge is associated with the changing drain voltage through the device’s gate-drain capacitance, so the driver’s current is largely supporting the drain transition during this interval.

The plateau’s level and duration are not universal constants. They vary with operating conditions, device characteristics, gate-drive impedance, and the current being switched. Compare captures only when the circuit conditions and probe setup are sufficiently similar.

Watch the current path as VDS falls. In a switching leg, current may transfer between the MOSFET and another device or freewheeling path. The load current and topology determine what commutates; the MOSFET waveform alone does not explain the full event.

The gate reaches its drive voltage

After the Miller interval, VGS rises toward the driver’s commanded level. The channel becomes more strongly enhanced, and the on-state resistance approaches the value associated with the actual gate voltage and junction temperature.

Check that the gate drive matches the device’s datasheet conditions for on-resistance and gate limits. A waveform that reaches a voltage above threshold may still not reach the intended operating point. Conversely, do not exceed the specified gate-source limits while seeking a lower conduction drop.

Read the conduction interval

During conduction, an enhanced channel carries load current and the MOSFET has a voltage drop across drain and source; the level depends on current, gate drive, temperature, and the device. Use the flat portion of the waveform to assess on-state behavior, not the switching edge.

First confirm that the device is fully driven for the operating condition. Then compare VDS and ID during the interval when the MOSFET is carrying current. In a simple resistive approximation, the conduction drop is related to current and on-resistance, but the resistance changes with temperature and gate voltage. The datasheet’s specified conditions matter when comparing a measured waveform with a nominal value.

Also distinguish MOSFET current from load current. During dead time or a commutation interval, another element may carry some or all of the load current. In a switching converter, the current path can change at the same time as the MOSFET voltage changes, so inspect the circuit diagram alongside the traces.

For a foundation on device structure and operation, see power MOSFET operation. When applying that foundation to a measured waveform, check whether the device is in its intended on-state, whether current has settled, and whether the observed voltage includes wiring or measurement effects.

Conduction loss is commonly assessed from the device’s on-state voltage and current over the interval, while switching loss is associated with voltage and current overlapping during transitions. A waveform can help identify those intervals, but a loss estimate also needs representative operating conditions and device data. Do not infer an average loss from one edge without accounting for switching frequency and the full operating cycle.

Trace turn-off and current commutation

At turn-off, the driver removes gate charge, channel conduction decreases, and VDS rises as current transfers to the available commutation path. The load and circuit determine how that current moves, so interpret gate, drain, and current traces together.

Gate discharge begins

When the driver commands turn-off, it draws charge from the gate. VGS falls, reducing channel strength; the MOSFET can continue carrying current while the gate voltage moves toward the Miller plateau.

The initial discharge rate depends on the driver’s ability to sink gate current and the total impedance in the gate loop. Gate resistance, driver output impedance, and parasitic inductance all influence the observed edge. If the gate trace falls slowly, check the drive path before attributing the behavior solely to the MOSFET.

Drain voltage rises at the Miller plateau

During the turn-off Miller interval, VGS may remain relatively flat while VDS rises. As the drain voltage changes, current transfers away from the channel into another available route, such as a freewheeling path in an inductive switching circuit.

The shape of this transition depends on load current and the impedance of the commutation loop. Inductive current cannot change instantaneously, so the circuit must provide a path for it. If that path is absent or poorly characterized, the drain waveform may show overshoot or ringing rather than a clean transition.

Compare the rise in VDS with the current trace. A rising drain voltage does not automatically mean load current has stopped; current may be flowing elsewhere in the circuit. Verify where the current probe is placed and which branch it measures.

The device reaches its off state

Once the gate has discharged below the channel’s effective conduction region, the MOSFET is off and supports drain-to-source voltage, subject to the circuit’s operating conditions. The gate should settle at its intended off-state level without unintended re-turn-on.

Check for gate bounce after the main edge. A rapid drain-voltage change can couple through the gate-drain capacitance and disturb VGS, especially when the gate loop has significant impedance. The result can be a brief gate excursion even though the driver has issued an off command. Review the measured gate voltage at the device, not only the driver output.

Check parasitics and switching-waveform pitfalls

Unexpected overshoot, ringing, or edge shape often reflects the interaction of circuit parasitics, device capacitances, gate drive, and measurement setup. Compare the waveform with the schematic and probe arrangement before changing the MOSFET or driver.

Account for inductance and capacitance

Stray inductance in the power loop produces voltage when current changes, while capacitance stores and exchanges charge as circuit voltage moves. Together, they can create drain overshoot and ringing around switching edges. The MOSFET’s own capacitances participate in these transitions; the observed waveform reflects the complete circuit, not the device in isolation.

Inspect the loop that carries the fastest-changing current. Long connections and separated supply-return paths can add inductance. Then check whether ringing appears at both turn-on and turn-off, and whether it changes with load or switching conditions. Those comparisons help distinguish a repeatable circuit response from a one-off capture artifact.

Do not equate every peak with the MOSFET’s steady-state blocking voltage. Use the datasheet’s ratings and the application’s actual waveform conditions to assess the device’s operating margin. A qualified power-electronics engineer should review energized high-voltage measurements and design-specific operating limits.

Check gate-drive and load effects

The driver, gate resistance, and gate-loop layout influence how quickly charge enters or leaves the gate. Changing gate resistance can alter edge speed, but it can also change switching loss and the tendency to excite ringing. Treat it as a design variable to evaluate against measured behavior, not as a universal fix.

Load type matters too. A resistive load and an inductive load do not produce the same current transition when the MOSFET switches. In an inductive circuit, identify the current path during each edge and confirm whether another device is conducting. A current trace that does not match the expected path may indicate a measurement-point or circuit-interpretation problem.

When comparing MOSFET options, check the voltage rating, package, gate-drive requirements, on-resistance conditions, and switching-related data in the relevant datasheet. A requested rating or package is a selection constraint, not evidence that a particular device fits the circuit without further review.

Measure waveforms without misleading artifacts

A trustworthy capture requires measuring the right nodes with a suitable probe connection. Use the MOSFET’s source as the reference for VGS, and minimize the probe-loop area when measuring fast transitions. A long ground lead can pick up noise and make ringing appear larger or more complex than the voltage at the device terminals.

For VDS, connect across the device’s drain and source with a measurement method appropriate to the voltage and transient conditions. Confirm probe bandwidth and attenuation settings, and keep the measurement points consistent across captures. For current, verify the probe direction and whether it surrounds the MOSFET branch, the load branch, or the whole commutation loop.

Capture gate voltage, drain voltage, and current against the same time reference. If an edge looks inconsistent with the circuit, repeat the measurement after checking probe connections and grounding. Never interpret a trace without recording where and how it was measured.

Use the waveform to guide your next design check

A switching waveform is most useful when you relate each transition to the gate drive, load current, commutation path, and measurement setup. Use that sequence to identify which design condition needs checking, then compare the device’s datasheet specifications with the circuit requirements.

Work through the capture in order:

1. Confirm VGS is measured relative to the MOSFET source and reaches the intended drive levels.
2. Identify threshold crossing, the Miller plateau, the VDS transition, and the settled conduction interval.
3. Trace the load current through the circuit during turn-on, conduction, and turn-off.
4. Check overshoot and ringing against loop parasitics and the measurement setup.
5. Compare the observed operating conditions with the device datasheet, including voltage rating, package, gate-drive conditions, and on-resistance.

This process makes the working of a power MOSFET easier to interpret without treating one waveform as a complete device assessment. If a transition remains unexplained, revisit the circuit’s current path and measurement points before making a component or gate-drive change.